Mr. Jagannatha K B

B E M Tech, (PhD) , Assistant Professor

Got my bachelor's degree B.E. (Electronics and Communication Engineering) from Sapthagiri college of engineering, Bangalore, VTU, in the year 2007. M.Tech (Microelectronics Circuit and VLSI Design) degree from NIT Calicut, kerala in the year 2009. Currently, working as Assistant Professor in Department of Electronics and Communication Engineering, BMSIT&M since 2009. Pursuing PhD in the area of Amorphous Materials application in Phase change memory from VTU. 16 publications in reputed International Journals and International/National Conferences. received best paper award for the title "ASIC core design of LOW power AES algorithm", from JAIN UNIVERSITY. Research interest lies in the field of Thin film coating, synthesis of bulk material and preparation of thin film, fabrication of memory device and CMOS VLSI Design.

Phone: 9972811552     Email:


Teaching : 8
Research : 5

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  • Thin film coating, VLSI Design,verilog HDL

Memberships in professional bodies

  • MRSI
  • IEEE


  • VLSI Front end & Back End design
  • C, C++
  • HDL
  • Thin film coating

Workshops/Conferences/Seminars conducted

  • TEQIP-II sponsored one week short term course/workshop on “ Emerging Trends in VLSI” -
  • Advanced Controllers -
  • Nano technology -
  • Two Week ISTE STTP on CMOS, Mixed signal and Radio Frequency VLSI Design conducted by IIT Kharagpur, India -

Courses Taught

  • Digital electronics
  • control systems
  • Basic electronics
  • Electronics instrumentation
  • Programming using C++
  • Digital design using of VHDL
  • Optical fiber communication
  • analog and digital electronics
  • fundamentals of HDL

Additional Responsibilities

  • NAAC single point coordinator
  • Dept. Prcotor coordinator
  • Dept. Hosue keeping incharge
  • Dept. Electrical maintenance
  • Anti Ragging commitee member
  • NBA criteria 5


Journal Name Journal Type Volume Number Issue Number ISSN ISBN Paper Title
World Journal of Science and Technology International 2 5 ASIC core design for low power AES
IFRSA International Journal Of Computing International 2 3 FPGA and ASIC implementation of Vedic Multiplier
International Journal of VLSI System Design and Communication Systems International 2 4 2322-0929 Efficient Design of sequential counters using Reversible Logic Gates
International Journal of Engineering Science Invention International 2 12 2319 – 6734 Fpga Implementation of Truncated Multiplier Using Reversible Logic GatesUsing Reversible Logic Gates